| 000 | 00648nam a2200241Ia 4500 | ||
|---|---|---|---|
| 008 | 240107s9999 xx 000 0 und d | ||
| 020 | _a9.78813E+12 | ||
| 082 | _a621.392 CIL | ||
| 082 | _bCIL | ||
| 100 | _aCILETTI MICHAEL D | ||
| 245 | 0 | _a"MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL" | |
| 245 | 0 | _a"MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL" | |
| 250 | _n1st | ||
| 260 | _aNEW DELHI | ||
| 260 | _bPEARSON | ||
| 260 | _c1999 | ||
| 300 | _a727 | ||
| 365 | _b995 | ||
| 500 | _aUNDER TEQIP PHASE - II | ||
| 650 | _aELECTRONICS | ||
| 650 | _bMODELLING SYNTHESIS VERILOG HDL | ||
| 942 | _cREF | ||
| 999 |
_c16359 _d16359 |
||