DEFECT ORIENTED TESTING FOR NANO METRIC CMOS VLSI CIRCUITS DEFECT ORIENTED TESTING FOR NANO METRIC CMOS VLSI CIRCUITS

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TextPublication details: NEW DELHI; SPRINGER; 2010Edition: Description: 328ISBN:

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Cover image	Item type	Current library	Home library	Collection	Shelving location	Call number	Materials specified	Vol info	URL	Copy number	Status	Notes	Date due	Barcode	Item holds	Item hold queue priority	Course reserves
	Reference	Central Library, Aditya Institute of Technology and Management	Central Library, Aditya Institute of Technology and Management			621.397 SAC (Browse shelf(Opens below))					Not for loan			42994

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