TY  - BOOK
AU  - CILETTI MICHAEL D
TI  - "MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL"
SN  - 9.78813E+12
U1  - 621.392 CIL 
CY  - NEW DELHI
KW  - ELECTRONICS
KW  - MODELLING SYNTHESIS VERILOG HDL
N1  - UNDER TEQIP PHASE - II
ER  -