CILETTI MICHAEL D <br/><br/>
"MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL" "MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL" 

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 - NEW DELHI  PEARSON  1999 
 - 727 
<br/><br/> UNDER TEQIP PHASE - II 
<br/><br/><label>ISBN: </label>9.78813E+12 
<br/><br/><label>Subjects--Topical Terms: </label><br/>ELECTRONICS MODELLING SYNTHESIS VERILOG HDL 
<br/><br/><label>Dewey Class. No.: </label>621.392 CIL  / CIL