SACHDEV MANOJ <br/><br/>
DEFECT ORIENTED TESTING FOR NANO METRIC CMOS VLSI CIRCUITS DEFECT ORIENTED TESTING FOR NANO METRIC CMOS VLSI CIRCUITS 

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 - NEW DELHI  SPRINGER  2010 
 - 328 
<br/><br/> UNDER TEQIP PHASE -II 
<br/><br/><label>ISBN: </label>8184894295 
<br/><br/><label>Subjects--Topical Terms: </label><br/>ELECTRONICS DEFECT ORIENTED TESTING NANO METRIC CMOS VLSI CIRCUITS 
<br/><br/><label>Dewey Class. No.: </label>621.397 SAC  / SAC