"MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL" "MODELING, SYNTHESIS, AND RAPID PROTOTYPING WITH THE VERILOG HDL"

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TextPublication details: NEW DELHI; PEARSON; 1999Edition: Description: 727ISBN:

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Holdings
Cover image	Item type	Current library	Home library	Collection	Shelving location	Call number	Materials specified	Vol info	URL	Copy number	Status	Notes	Date due	Barcode	Item holds	Item hold queue priority	Course reserves
	Reference	Central Library, Aditya Institute of Technology and Management	Central Library, Aditya Institute of Technology and Management			621.392 CIL (Browse shelf(Opens below))					Not for loan	TEQIP EEE		45811

UNDER TEQIP PHASE - II

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