| Cover image | Item type | Current library | Home library | Collection | Shelving location | Call number | Materials specified | Vol info | URL | Copy number | Status | Notes | Date due | Barcode | Item holds | Item hold queue priority | Course reserves | |
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Central Library, Aditya Institute of Technology and Management | Central Library, Aditya Institute of Technology and Management | 621.395 ABR (Browse shelf(Opens below)) | Not for loan | M. TECH VLSI | 16539 | ||||||||||||
Reference
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Central Library, Aditya Institute of Technology and Management | Central Library, Aditya Institute of Technology and Management | 621.395 ABR (Browse shelf(Opens below)) | Not for loan | M. TECH VLSI | 16540 |
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| 621.392 ROT PRINCIPLES OF DIGITAL SYSTEMS DESIGN USING VHDL | 621.392 ROT PRINCIPLES OF DIGITAL SYSTEMS DESIGN USING VHDL | 621.392 SUB DIGITAL CIRCUIT DESIGN THROUGH VERILOG HDL | 621.395 ABR DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN | 621.395 ABR DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN | 621.395 ABR DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN | 621.395 ABR DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN |
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