VLSI DESIGN MATHODOLOGIES FOR DIGITAL SIGNAL PROCESSING ARCHITECTURES (Record no. 15009)

MARC details
000 -LEADER
fixed length control field 00646nam a2200241Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 240107s9999 xx 000 0 und d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 88181283160
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.382 2 BAY
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Item number BAY
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name BAYOUMI MAGDY A
245 #0 - TITLE STATEMENT
Title VLSI DESIGN MATHODOLOGIES FOR DIGITAL SIGNAL PROCESSING ARCHITECTURES
245 #0 - TITLE STATEMENT
Title VLSI DESIGN MATHODOLOGIES FOR DIGITAL SIGNAL PROCESSING ARCHITECTURES
250 ## - EDITION STATEMENT
-- 1st
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. DELHI
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Name of publisher, distributor, etc. SPRINGER
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2009
300 ## - PHYSICAL DESCRIPTION
Extent 399
365 ## - TRADE PRICE
Price amount 695
500 ## - GENERAL NOTE
General note UNDER TEQIP PHASE -II
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element ELECTRONICS
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term following geographic name entry element ARCHITECTURE VLSI DIGITAL
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Reference
Holdings
Date last seen Total checkouts Full call number Barcode Cost, replacement price Price effective from Koha item type Lost status Damaged status Not for loan Withdrawn status Home library Current library Date acquired Source of acquisition Cost, normal purchase price Bill No Bill Date
07/01/2024   621.382 2 BAY 42940 695.00 07/01/2024 Reference         Central Library, Aditya Institute of Technology and Management Central Library, Aditya Institute of Technology and Management 07/01/2024 PARAMOUNT BOOK DISTRIBUTORS 695.00 PBD 2422 08-08-2014